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What is
GA9354C
?
The GA29F040 is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. Flash memories offer the most cost-effective and reliable read/write non volatile random access memory. The GA29F040 is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard GA29F040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the GA29F040 has separate chip enable (CE#) and output enable (OE#) controls.
Flash memories augment EPROM functionality with incircuit electrical erasure and programming. The GA29F040 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. Flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and program mechanisms. In addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The GA29F040 uses a 5.0V 10% VCC supply to per- form the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.
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Single +3V power supply Low insertion loss: 0.5 dB @ 2000 MHz
High isolation of 30 dB @ 2000 MHz Typical input P1dB compression point of +40 dBm
100 krad(Si) total dose Single-pin CMOS or TTL logic control
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Pin Configuration
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Functional Diagram
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 |
 |
Table 1. AC Electrical Specifications @ –40 °C to +85 °C, VDD = 3.0V (ZS = ZL = 50Ω)1
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Parameter
|
Condition
|
Min
|
Typ
|
Max
|
Unit
|
|
Operation frequency 2 DC 6000
|
DC
|
6000
|
MHz
|
||
|
Insertion loss
|
2000 MHz
|
0.5
|
0.70
|
dB
|
|
|
Isolation – RFC to RF1/RF2
|
2000 MHz
|
40
|
45
|
dB
|
|
|
Isolation – RF1 to RF2
|
2000 MHz
|
32
|
35
|
dB
|
|
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Return loss3
|
2000 MHz
|
20
|
dB
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||
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Input P1dB compression point
|
2000 MHz
|
28
|
30
|
dBm
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Notes: 1. Parameters are tested in production at –40 °C and +85 °C.
2. Device linearity will begin to degrade below 10 MHz.
3. Return loss not measured in production due to equipment limitations.
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Table 2. Pin Descriptions
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Table 3. DC Electrical Specifications
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Pin #
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Pin Name
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Description
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Parameter
|
Min
|
Typ
|
Max
|
Unit
|
|
| 1 |
VDD
|
Nominal +3V supply connection
|
Supply voltage, VDD
|
2.7
|
3.0
|
3.6
|
V
|
|
| 2 |
CTRL
|
CMOS or TTL logic level:
High = RFC to RF1 signal path.
Low = RFC to RF2 signal path.
|
Input leakage
|
–1
|
1
|
μA
|
||
| 3 |
GND
|
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
|
Supply current, IDD (VDD = 3V, VCTRL = 3V) |
μA
|
||||
| 4 |
RFC
|
Common RF port for switch.*
|
Control voltage high
|
V
|
||||
| 5 |
RF2
|
RF2 port.*
|
Control voltage low
|
V
|
||||
| 6 |
GND
|
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
|
Absolute maximum ratings are those values listed in the following table.
Exceeding these values maycause permanent device damage.
Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute
maximum ratings for extended periods may affect device reliability.
|
|||||
| 7 |
GND
|
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
|
||||||
| 8 |
RF1
|
RF1 port.*
|
Table 4. Absolute Maximum Ratings
|
|||||
|
GND
|
GND
|
Bottom of the package is ground.
Connecting the bottom of the package to
ground is required
|
Symbol
|
Parameter/Condition
|
Min
|
Max
|
Unit
|
|
|
Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. Latch-Up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. |
VDD
|
Power supply voltage
|
–0.3
|
5.0
|
V
|
|||
|
VI
|
Voltage on any input except for the CTRL input
|
V
|
||||||
|
VCTRL
|
Voltage on CTRL input
|
5.0
|
V
|
|||||
|
TST
|
Storage temperature range
|
–65
|
+150
|
°C
|
||||
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Table 5. Control Logic Truth Table
|
TOP
|
Operating temperature range
|
–40
|
+105
|
°C
|
|||
|
Control Voltage
|
Signal Path
|
PIN
|
Input power (50Ω,CW)
|
35
|
dBm
|
|||
|
CTRL = CMOS or TTL High
|
RFC to RF2
|
ΘJC
|
Theta JC
|
57
|
°C/W
|
|||
|
CTRL = CMOS or TTL Low
|
RFC to RF1
|
Tj
|
Junction temperature
|
+125
|
°C
|
|||
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The control logic input pin (CTRL) is typically driven by a +3V CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.)
|
VESD
|
ESD voltage
(Human Body Model)
|
200
|
V
|
||||
|
TID
|
Total cumulative exposure to
ionizing radiation
|
100
|
kRad(Si)
|
|||||
Typical Performance Data @ VDD= 3V
Figure 14. Package Drawing (dimensions are in millimeters)
8-lead CFP
Note: Bottom of the package is ground. Connecting the bottom of the package to ground is required
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