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Variable Gain Amplifier

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Variable Gain Amplifier

Product

 
to ReplaceFrequency (GHz)ChannelsMax Gain
(dB)
Max Gain control range
(dB)
Step forward
(dB)
Noise figure
(dB)
Channel Isolation 
(dB)
Input
VSWR
Output
VSWR
P-1
 (dBm)
OIP3 (dBm)Power consumption
(V/mA)
Size
(mm)
GAG0201HMC6810.1~2.013831.50.52.5-1.51.52137+5V /160uA5.0×5.0×0.85 LGA 
GAG0202RFDA00470.4~3.8214.331.50.53.5501.21.52138.6+5V /168 mA7.0×7.0 LGA 
GAG0203-1.3~2.8426.531.50.59392.12.11730+3.3V/420mA8.0×8.0×0.81 LGA 
GAG0204BGU8822/A0.4~2.62373110.8501.61.42233+5V /240 mA5.0×5.0×0.73 LGA 
GAG0204-0.4~1.1428.531.50.511451.61.81835+3.3V/400mA8.0×8.0×0.73 LGA 
GAG0206TQC93110.4~3.8214.431.50.53.7551.31.42136+5V /168 mA7.0×7.0 LGA 

 

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GA29F040


The GA29F040 is a 4-mega bit Flash memory organized as 512K bytes of 8 bits. Flash memories offer the most cost-effective and reliable read/write non volatile random access memory. The GA29F040 is packaged in 32-pin PLCC, TSOP, PDIP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard GA29F040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the GA29F040 has separate chip enable (CE#) and output enable (OE#) controls. Flash memories augment EPROM functionality with incircuit electrical erasure and programming. The GA29F040 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. Flash technology reliably stores memory con- tents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and program mechanisms. In addition, the combi- nation of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The GA29F040 uses a 5.0V 10% VCC supply to per- form the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

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